1. Field
The embodiments discussed herein are directed to a delay circuit for generating minute delay times.
2. Description of the Related Art
As circuits for generating minute delay times, circuits constructed by series-connecting unit delay devices, each of which generates a minimum unit delay time, to form a plurality of stages have been proposed. In such circuits, it is possible to vary the generated delay times by adjusting the number of connected unit delay device stages.
In such delay circuits, to reduce error between a desired delay time and an actual generated delay time, it is effective to shorten the delay time of the unit delay device. However, shortening the delay time of the unit delay device increases power consumption by the unit delay devices. Consequently, the power consumption of semiconductor integrated circuit devices including such delay circuits increases.
To deal with this, Japanese Patent Application Laid-open No. H6-21761 discloses a delay circuit which reduces the error in the generated delay time while suppressing the increase in power consumption. This delay circuit includes a circuit having a single delay circuit which generates a unit delay time T connected in series with a plurality of delay circuits which each generate a double unit delay time 2T and a circuit having a plurality of series-connected delay circuits which generate a unit delay time 2T, and through parallel operation of the two circuits, allows generation of delay times of 2T, 3T, 4T, 5T . . . .
With such a construction, since it is possible to generate the delay times 2T, 3T, 4T, 5T . . . with only a single delay circuit generating the unit delay time T, a reduction in power consumption can be realized.
However the delay circuit disclosed in the Japanese Patent Application Laid-open No. H6-21761 has a problem in that it is necessary to constantly operate the circuit having the single delay circuit which generates the unit delay time T connected in series with the plurality of delay circuits which each generate a double unit delay time 2T and the circuit having the plurality of series-connected delay circuits which generate the unit delay time 2T, and consequently the power consumption remains high.
Moreover, since the delay circuit is constructed to select one of the delay times 2T, 3T, 4T, 5T . . . for output using a multiple input multiplexer, the time taken by multiplexer operations is a source of error in the delay time when generating minute delay times. The delay circuit has a further problem in that inclusion of the multi-input multiplexer causes an increase in circuit area.